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Freescale Semiconductor /MK61F15WS /DDR /CR56

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Interpret as CR56

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PHYUPDRESP0RESERVED 0RDLATADJ 0RESERVED 0WRLATADJ 0RESERVED

Description

DDR Control Register 56

Fields

PHYUPDRESP

TDFI PHYUPDRESP parameter
RESERVED

Reserved
RDLATADJ

Read Latency Adjust
RESERVED

Reserved
WRLATADJ

Write Latency Adjust
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data